资源列表
AdderSustract
- Adder-Substracter 4bits This code allows you add four bits variables or substract four bits variables. Include adder module, sbstracter module and mux2-1 module. -Adder-Substracter 4bits This code allows you add four bits variables or substract
Twobits-Adder
- Two bits Adder, this code allows add two bits variables using switches of FPGA, the result is shown in seven segments display. Include seven segments decoder module. The program was verified using BASYS 2 FPGA.
Security-System
- The security system implemented monitors the state of eight doors (open or closed) and shows the state in leds when the selector indicate it. Also the number corresponding to the desired door is shown in a 7seg display.
Frecuency-Divisor
- This code Use the 50 Mhz clock of BASYS 2 FPGA to generate a frecuency divisor (choose the div value using FPGA Switches). The result is shown in two leds to compare, one have a frecency fixed (with out div ) and the secon led showm the div selected
24
- 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
ins_Decoder
- 采用VHDL语言编写的矩阵变换器四步换流程序-matrix converter
RS485verilog
- 这是用Verilog写的RS485通信程序，可以使用，希望大家能够互相交流，-This is a Verilog writing RS485 communication program, can be used, I hope we can communicate with each other,
H891
- 基于ALTERA的NIOS系统的车载显示系统(车载摄像头和TFT显示器)设计源代码-Car ALTERA NIOS system based display system (car camera and TFT display) design source code
AD9548_Driver155555
- ad9548的详细驱动程序，非常全面，内含有测试图片，与大家交流。-ad9548 driver detailed, very comprehensive, containing the test images to share with you.
ones_counter
- 8bit 的计数器，如文件名所示microprogram_controlled_ones_counter_constraints_ise6_bak。VHDL-8bit counter, as shown in the file name. VHDL
Codes
- USB 2.0 using VHDL with files : main.c, drice.c and HIGH_SPEED_USB_CORE_SETUP_TRANSACTION
vga3_you
- VGA接口应用的VHDL语言编程， 已经通过实验验证-VGA interface application has been verified by experiment. . . . . . . . . . .