资源列表
DIRECT-DIGITAL-SYSTHESIZER
- Direct digital systhezier on FPGA WRITTEN WITH VERILOG
DDS
- DDS信号生成模块，使用MATLAB产生查找表，可输出方波、三角波、锯齿波、正弦波-DDS signal generator module, using MATLAB to generate a lookup table can output square wave, triangle wave, sawtooth, sine
8051
- VHDL语言编写的SW8051IP核，并加入ROM,RAM,RAMX,PLL模块，可下载HEX文件并验证成功-VHDL language SW8051IP nuclear and add ROM, RAM, RAMX, PLL modules, you can download the HEX file and verify success
cdma
- codes for fpga implementation of cdma system using verilog hdl.
ps2
- ps2键盘的驱动，可以在led上显示输出的键码-ps2 keyboard driver, you can display the output of the key code on the led
PWM
- 非常详细的PWM硬件语言程序，希望对大家有所帮助-Very detailed PWM hardware language program, we hope to help
nios_IRQ_verilog
- 基于veriog_nios硬件平台的中断实验源代码，希望对大家有所帮助-Interrupt-based hardware platform veriog_nios experiment source code, we hope to help
AD
- AD采集控制时序,控制对象AD1674启动和转换-AD acquisition control timing, control object AD1674 starts and conversion
counter
- 脉冲上升或下降沿个数计数功能，并且可以配置初态和触发计数条件-Pulse rise or fall along a counting function, and can be configured to initial and trigger conditions
digital_filter
- 数据滤波功能，可以配置滤波的宽度,或者向后推几个时钟-The data filtering function, can configure the filter width
MS_TMR
- 三模冗余设计，当某一位数据错误时，可以自动进行纠正-Three modular redundancy design, when a data error, can be automatically corrected
PPS
- 脉冲宽度可配置，输出不同脉宽值，启动后输出-The pulse width can be configured with different pulse width, output value