资源列表
Reg_4bit
- Uploaded code to design 4 bit register.
ADDER_4_BIT
- implement 4 bit add using vhdl
full_adder
- design full adder by vhdl
sourceCODE
- binary to grey grey to binary 8x3 encoder 2x4 decoder etc- binary to grey grey to binary 8x3 encoder 2x4 decoder etc..
lzrw1-compressor-core_latest.tar
- Lzrw1 压缩算法。spatan6上运行，有完整的仿真环境和代码testbench-Lzrw1 compression algorithm. runs on spatan6, a complete simulation environment and testbench code
S1_38YIMA
- 38译码器，用ISE12.3实现。用Verilog HDL语言编写-38 decoder implemented with ISE12.3. Written in Verilog HDL language
S2_counter
- 用verilog HDL语言编制的计数器，并且可以在开发板上以灯亮灭体现功能，Xilinx的Spartan6系列芯片。-Counter with verilog HDL language preparation, and the development board to be light reflected off function, Xilinx' s Spartan6 series chips.
S16_ADC
- 用Verilog HDL语言编写的AD转换器，可以再Xilinx芯片实现，用ISE软件环境下开发-Using Verilog HDL language AD converter, you can then Xilinx chip, with the ISE software development environment
ML605_uart
- 本案例是开发xinlinx ml605 FPGA上使用UART通信的简单例程-This case is the development of the xinlinx ml605 FPGA UART communication using simple routine
key_led1
- 简单的按键控制LED登，适合FPGA-Verilog初学者-Simple button control LED board, suitable for FPGA-Verilog beginners
vhdl
- 通过VHDL语言，实现简单的多路选择器、串行加法器、并行加法器、计数器-By VHDL language, a simple multiple-choice, serial adder, parallel adder, counter
fpga_code
- 神经网络ELM的vhdl实例，该算法权值已在matlab上训练好，实际就充当一个硬件分类器-Vhdl examples ELM neural network, which is a good weight algorithm has been trained on matlab, actually acts as a hardware classifier