资源列表
Lab12_shiftreg
- 4位移位寄存器的设计与实现.本实验中用Verilog语句来描述。nexy3.-Design and implementation of a 4 bit shift register. The Verilog statement in this experiment to describe. Nexy3
Lab13_mod5cnt
- 模-5计数器就是从0到4重复计数。也就是说，它一共要经历5个状态，输出从000变到100然后再回到000。本实验中用Verilog语句来描述。-Module-5 counter is from 0 to 4 repeat count. That is to say, it has to experience 5 state, the output from 000 to 100 and then to 000. Using the Verilog statement in this experi
Lab14_count3a
- 8分频器的设计与实现.8分频器的真值表，其最高位q2的输出就是对输入信号的8分频。本实验中用Verilog来实现。-Design and implementation of.8 8 frequency divider divider of the truth table, output the highest bit Q2 is the input signal frequency of 8. Use Verilog to achieve in this experiment.
Lab15_sw2reg
- 开关数据加载到寄存器并显示的设计与实现.3． 设计一个可以把4个开关的内容存储到一个4位寄存器的电路，并在最右边的7段显示管上显示这个寄存器中的十六进制数字。我们使用到去抖动模块clock_pulse， 用btn[0]作为输入；8位寄存器模块，用btn[1]作为加载信号；7段显示管上的显示模块x7segbc；分频模块clkdiv，用以产生模块clock_pulse和x7segbc的clk190时钟信号。-Design of switching data is loaded into the re
cores
- a core has been developed for your 32 bit fpu with a least 32x2 input 4 bit operator with round off and 32 bit output and 8 bit exeption data.
VHDL
- VHDL功能模块直接用。分有： 去抖，数码显示，任意分频。-VHDL modules directly. Points are: to shake, digital display, arbitrary frequency.
adder4
- 基于VHDL的4位加法器。 由4个一位全加器级联构成。-VHDL-based 4-bit adder. One consists of four full adder cascade.
Dlatch3
- 基于VHDL的触发器设计。 由一个电平触发的D触发器构成的上下边沿触发器。-Trigger-based VHDL design. Consists of a level-triggered D flip-flops up and down the edge of the trigger.
8051corelcd
- fpga上实现的51内核，带有LCD试验，顺利试验成功很好用。-on fpga implementation of 51 core with LCD test, successfully tested well with the smooth.
fulladder-using-half-adder
- half adder full adder using half adder in verilog
seven-segment-display
- seven segment diaplay
alarm_clock
- digital clock with alarm and control