资源列表
verilogclock
- 如果不考虑占空比，直接利用计数器来进行分频，则占空比会发生变化。下面程序实现1：1的三分频。-if not duty cycle directly counter to the use of sub-frequency, duty cycle will change. Below a program : a third of the frequency.
no1
- VHDL做的16位并行输入转16同步串行输出-VHDL to do 16-bit parallel input to 16 synchronous serial output
17_usb_device
- Ch376控制器的控制程序，用于完成USB接口-Ch376_controller code by Verilog，used in USB communication
trigger
- 用vhdl对于GAL22V10编程，实现触发器功能-Using VHDL for GAL22V10 programming, realize trigger function
UART_RX
- 自己用Verilog写的串口接收程序，有testbench，可实现单字节接收和连续接收，testbench可测功能-Own use Verilog write serial reception procedures, testbench, can achieve single-byte receive and continuous reception, testbench measurable function
renyimo
- 这是一个用VHDL编写的计数器，是一个任意模的计数器，不过是个异步的-This is a work written in VHDL counter, is an arbitrary module of the counter, but is an asynchronous
vhdl
- 交通灯的设计，是基于vhdl的控制程序设计。
ds18b20
- verilog编写的ds18b20温度传感器程序，可综合-ds18b20 program written in verilog
decoder
- A program for a simple decoder using ModelSim6
ADC0809VHDLcontrol
- 基于VHDL语言，实现对ADC0809简单控制。 -Based on the VHDL language, to achieve simple control of the ADC0809.
SensorIF
- Hi This Xilinx File-Hi This is Xilinx File
qjq
- 通过ISE软件采用VHDL语言实现1位全加器的功能-Through the ISE software using VHDL language a full adder function