资源列表
uart_tx
- 基于FPGA的串口发送模块设计及仿真,可移植代码-Design and Simulation of serial port sending module based on FPGA，portable code
FPGA-TLC5620
- 基于FPGA的线性序列机与串行接口DAC驱动设计-Design of DAC driver for linear sequence machine and serial interface based on FPGA
DDS-pulse-random
- 数字频率计，该代码可用于产生任意频率的脉冲-this code is used to generate pulse
A4_Vote4
- 一个基于FPGA的四人投票计票程序，程序语言使用Verilog，初学者适用-A FPGA based voting procedure for four people voting
FPGA
- 一种新型FPGA器件延时计算方法,讲解详实-A new FPGA device delay calculation method, explain the details
uart
- VHDL串口程序 波特率115200 功能：返回所发一字节数据的各位取反-UART BAUD 115200
ARM7VerilogCODE
- ARM7 Verilog代码及设计文档，文档说明比较详细-ARM7 Verilog u4EE3 u7801 u53CA u8BBE u8BA1 u6587 u6863 uFF0C u6587 u6863 u8BF4 u660E u6BD4 u8F83 u8BE6 u7E
digital_code_decode
- 基于FPGA的数字调制与解调 含fsk psk的调制与解调 fpga型号EP4CE6F17C8-fpga digital modulation
spi_test
- 基于FPGA的SPI通讯测试，可以一块FPGA单独测试，也可以2片FPGA对测。-SPI communication test, based on the FPGA can be a piece of FPGA test alone, can also be 2 piece of FPGA for measurement.
PipelineCPU
- 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU，含代码工程文件和相关设计说明文档，比较详细。-verilog HDL, 32 MIPS pipeline CPU
RQDQ-4
- 4人抢答器，计时器和抢答器综合，开始抢答时，计时器从20s开始倒计时，如果无人抢答，计时器到0时报警器响3s，有人抢答，数码管会显示第几人抢答。-4 hours of answering device, timer and answer device synthesis, began to answer, the timer 20s countdown, if no one answer, the timer to 0 when the alarm ring 3s, some people a
8051
- fpga移植51单片机内核,完全兼容51单片机的开发环境-Fpga u79FB u690D1 u5355 u7247 u673A u5185 u6838, u5B8C u5168 u517C u5BB1 u5355 u7357 u673A u7684 u5F00 u53D1 u73AF u5883