资源列表
clock_time
- 本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
t1935
- 1935有限状态机 四个状态 一般有限状态机的设计-1935 finite state machine four state
jingsai
- 微机原理课程实验应用，竞赛抢答器的设计，文本档-Microcomputer Principle Course Laboratory applications, Contest Responder design, text files
bmul32
- 用VHDL写的一个32位并行乘法器的源代码，已经过验证，可以直接使用
ADPCMDecoder
- ADPCM decoder working on Xilinx ISE 12.2 code includes core ICON ILA VIO test on chipscope
2dpsk-modulation
- 2dpsk fpga各个模块的实现代码，分开书写-2dpsk modulation code
counter1
- vhdl 计数器源程序，大家看看吧 vhdl 计数器源程序，大家看看吧-vhdl counter source, we see it vhdl counter source, we see it
I2C_slaver
- I2C从端，用于接收master的控制信号 verilog-I2C from the side, for receiving master control signal verilog
mux6
- 多路开关程序，verilog HDL编写，在FPGA里面实现，已经通过。-writing by verilog HDL program for FPGA application,complied successfully.
fir6dlms
- lms的verilog代码，我找了好久在才找的的，好东西，大家一起学习
fir.rar
- fir滤波器，Verilog语言写的，容易看懂,fir filter, Verilog language written in easy to understand
floatadd
- 32位浮点数加法，使用的语言是verilog。其中包括的是工程中的v文件。-32-bit floating-point addition, the use of language is verilog. Including is v of the engineering documents.