资源列表
Verilog
- 第1章 Verilog HDL入门2008 第2章 Verilog的模块2008 第3章 Verilog的基础知识2008 第4章 Verilog的语句2009-Chapter 1 Introduction to Verilog HDL Verilog 2008, Chapter 2, Chapter 3 of the module in 2008 the basics of Verilog 2008, Verilog statements in Chapter 4, 2009
Lcd-12864
- 这是一个用ALTER公司FPGA控制外部128×64液晶的程序，很实用，希望大家下载！-This is a company with FPGA control ALTER external 128 × 64 LCD procedures, it is useful, I hope you download!
xapp774
- 基于tus5000评估板的VHDL源代码，用于超声波检测，xinlinx提供的-Based on the VHDL source code tus5000 uation board, used in ultrasonic testing, xinlinx provide
Counter8bit
- This is an 8 bit Up Counter coded using Verilog HDL. Bus width can be edited to your desired specs.
Ethernet_Accel_Design
- altera官方以太网例程（基于niosII）-Accelerating Nios II Ethernet Applications User Guide
FPGA-_control_DM9000A-Ethernet
- FPGA控制网口芯片DM9000A进行以太网传输数据。-The FPGA control network port chip the DM9000A Ethernet transmission data.
clock-with-alarm-and-timer
- FPGA example, the timer buzzer. Can learn the FPGA involved in the grammar!-FPGA example, the timer buzzer. Can learn the FPGA involved in the grammar!
DM9000A
- 详细描述了DM9000A网络接口芯片的功能，对于DE2开发板上的学习很有帮助。还上载了C程序的实现以及Verilog 代码的实现，
LD
- verilog语言实现LD灯的轮流点亮，下载到板子，验证了的。下载即可在ISE中实现仿真。-verilog language LD lights turn lights, downloaded to the board to verify the. Downloads can be realized in the ISE simulation.
clock-with-alarm-and-timer
- 黑金EP2C5QC808N系列，Quartus 11.0 中编译综合的数字钟，具有实时时钟运行，时钟校准，整点报时以及定时提醒功能，包含全部的工程文件。-Black EP2C5QC808N series, Quartus 11 compilation and synthesis of digital clock, with real-time clock operation, calibration of the clock, the whole point timekeeping, timin
adjustable-signal-generator
- 这是一个可调的信号发生器,可产生正弦波,矩形波,三角波,用SignalTap II 仿真 -This is an adjustable signal generator, can produce sine, square wave, triangle wave, with the SignalTap II simulation
PCt
- 这是关于赢vhdl语言变得信号采集卡，很有实用性，大家可以来看看的。