资源列表
DDS-SIN
- 用verilog语言实现DDS的正弦波发送-DDS sine wave sent verilog language
Use-FPGA-24KHZ-27KHZ-sine-wave
- 使用FPGA产生24KHZ到27KHZ的正弦波，步进为20HZ，可以通过按键调节-Use FPGA to generate a 24KHZ 27KHZ sine wave, stepping 20HZ, key adjustment
Verilog-HDLProgramming
- FPGA Verilog HDLProgramming FPGA设计电子书-FPGA Verilog HDLProgramming FPGA design books
booth
- booth乘法器的设计，里面内容详细，很适合新手学习-booth multiplier design, which detailed, it is suitable for novice learning
i2C
- FPGA入门教程----I2C实验，适合新手入门-FPGA Tutorial---- I2C test for Getting Started
dds
- 在quartus下的DDS设计，Verilog语言，可以产生正弦波、三角波、方波等，频率可调。-Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
quartuswork
- vhdl入门实例，一位全加器和一位半加器的quartus9.1程序，可直接运行(VHDL entry examples, a full adder and a half adder quartus9.1 program, can be run directly)
FIR
- The FIR digital filter algorithm is simulated and synthesized using VHDL
Nios_II-Handbook
- FPGA嵌入式nios CPU开发的资料，NIOS II开发的用户数据手册-Nios_II_Software_Developer s_Handbook，good
2048Mb_ddr2_verilog_model
- ddr2 verilog model,用于验证DDR2 Controller。-DDR2 Verilog model, and used to verify the DDR2 Controller.
z80control_latest.tar
- z80控制器,内部包含VHDL源代码,FOF文件,基于USB借口的设计实例等.-z80 controller contains the VHDL source code inside, FOF files, USB-based design example of such an excuse.
spiV
- FPGA spi通信协议，很全，大家参考，希望对大家有用。-Fpga spi Communication protocol, very full, we refer to the hope that useful.