资源列表
CLKCP01
- 液晶显示器320*240脉冲实现，每出现12个clk出一个字节脉冲，每出现40个字节脉冲出一个行脉冲。240行结束出一个帧脉冲.-LCD 320 * 240 pulse realized there every 12 clk byte out a pulse, with each 40-byte burst out a pulse line. 240 firms from the end of a frame pulse.
VHDL-Waveform-source
- I/V转换波形输出,可生成三角波、锯齿波、方波、和正弦波等常用波形。-I/V converter output waveforms can be generated triangle wave, sawtooth wave, square wave, and other commonly used sine wave.
FPGApabiao
- fpga跑表例子Altera DE2 quartus60-fpga Altera DE2 quartus60
adc
- 基于vhdl语言的adc调试程序，程序可移植性强，经过实际检测正确-Based on the adc vhdl language debugger, program portability, right after the actual testing
dianti
- VHDL程序电梯控制器。可完成6层楼的电梯控制。-Elevator controller VHDL procedures. To be completed by 6-story elevator control.
jishuqi
- 主要是采用了元件例化的方式来实现十进制的一个计数器-Mainly patients with a component-based approach to achieve a decimal counter
H_480
- 在spartan3开发板上实现了VGA 图像现实，代码简单实用，是源码。-In spartan3 development board to achieve a VGA image reality, the code is simple and practical, is the source code.
timespace_insert
- 本代码用于在两个数据报文之间插入一个周期的时钟间隔，使得后续的处理不会将报文头部丢弃
counter8
- this is a souce code for 8 bit counter
CRC_chk
- mac_rx code which is used sgmii mac recived .
___parallel_add0
- sum ololo bugaga altera master quartus do you need more?
p3structural
- To Design 1-bit Full Adder using Verilog HDL for all logic gates with switch and gate level modelling.