资源列表
web_cpu88.zip
- Intel微处理器8088的VHDL实现，可以用ModelSim进行仿真测试。,Realization of intel microprocessor 8088 in VHDL language, and can be tested and simulated with ModelSim.
saa7113.rar
- saa7113配置，verilog语言写的 挺好的，直接可以加入,saa7113 configuration, verilog language of good and can be added directly
shuzixiangweibiao.rar
- 数字相位表，实现两个信号的鉴相。输入信号，输出相位差,VHDL、ISE、MODELSIM
Extended_Application_Interface
- BJ-EPM240V2实验例程以及说明文档实验之十二接口扩展应用,BJ-EPM240V2 experimental test routines as well as documentation of the expansion of the application interface
BJ-EPM_entire_board_test_code.
- BJ-EPM240V2实验例程以及说明文档实验之BJ-EPM整板测试用代码,BJ-EPM240V2 experimental test routines as well as documentation of the entire board BJ-EPM test code
Schematic_BJ_EPM240V2.rar
- BJ-EPM240V2实验例程以及说明文档实验之BJ_EPM240V2原理图,BJ-EPM240V2 experimental test routines as well as documentation of schematics BJ_EPM240V2
shixian.rar
- 该文件是一份本人设计的实验报告，报告内详细说明了用VHDL语言，设计一个三位动态显示的计数器。采用模块化得设计，设计通过了仿真以及下载实现。总的文件是：shixian.vhd,下面包括四个元件：jishu1000.vhd,xzqh.vhd,senvedec.vhd,disp.vhd.,this paper uses vhdl to complement a design about how to make three leds display at the same time.
add.rar
- 流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）,Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
B.rar
- altera usb下载线原理图和cpld程序,altera usb download cable schematics and procedures cpld
ADPLL.rar
- 全数字锁相环（adpll)的部分源程序代码，是其中最重要的部分。,All-digital phase-locked loop (adpll) part of the source code, is one of the most important part.
RSC.rar
- Turbo码编码器的两个分量编码器RSC，主要由四个移位寄存器和两个模2加法器组成,Turbo code encoder of the two component encoders RSC, mainly by the four shift register and the two-mode adder composed of 2
vhdl_model.rar
- VHDL实例，各个方面均有，基本语法，状态机，汉明码，寄存器，步进电机控制器，表决器，多路选择器，译码器等等,VHDL model,include: basic grammer,moore mealy state machine,register,counter,multi,decoder,et..