资源列表
sd_reader.rar
- SD卡读卡器模块的VHDL及软件驱动代码，可作为外设挂接在Avalon总线上。支持以SD模式、4线模式读取。在24MHz时钟驱动下读取速率可达8MByte/s,SD card reader module and software drivers VHDL code, can be articulated as a peripheral bus in Avalon. To support the SD model, 4-wire mode read. Driven by the 24MHz clo
leon-2.2.tar.gz
- 宇航级微处理器LEON2 2.2 VHDL源代码,很难找的.,Aerospace-grade microprocessor LEON2 2.2 VHDL source code, it is difficult to find.
quartusII8.0_crack.rar
- quartusii8.0正式版破解器,正式版可到官网去下载。http://www.altera.com.cn/,quartusii8.0_crack
ethernet.zip
- 以太网控制器VHDL实现以及相关参考文档，超有使用价值，请仔细阅览,ethernet MAC controller VHDL realize
vga_hex_disp.rar
- 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。,The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compilin
pcicard.rar
- pci debug card 的VHDL源代码,pci debug card of the VHDL source code
grain.rar
- Grain流密码的ＶＨＤＬ源程序，具体说明见 www.ecrypt.eu.org/stream/grainp3.html,The Grain cipher documentation can be obtained at www.ecrypt.eu.org/stream/grainp3.html
SPIsend.rar
- Verilog HDL的程式，上網找到SPI程式， vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！,Verilog HDL programs, Internet find SPI program, vspi.v this very useful progra
wishbone_VHDL.rar
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流,Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
pipeline.rar
- 关于FPGA设计中的流水线技巧的使用和例子，一个很好的减少硬件消耗的技巧,About FPGA design using pipelining techniques and examples, a good technique to reduce the hardware consumption
Max_PlusII_ppt.rar
- Max+Plus II 的ppt文档，看后可以很轻易上手Max+Plus II,Help
usart.rar
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order. ,USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.