资源列表
8-bit-Multiplier
- Multiplication is performed in three stages. After reset, the 8-bit operands are “loaded” and the product register is set to zero. In the second stage, s1, the actual serial-parallel multiplication takes place. In the third step, s2, the product is t
VHDL-Design-of-31-bit-Pipelined-Adder
- The design runs at 316.46 MHz and uses 125 LEs.
cy4ex14
- 超声波测距，包括分频模块均值滤波模块计算距离模块-verilog fpga
Basic_Examples
- Basic syntax and codes used in VHDL
Mealy
- Example of Mealy sequence in VHDL
Vending-Machine-using-Moore
- Vending Machine simulation using Moore sequence
usart_txd_mk3
- 使用Verilog写的串口发送程序，希望对大家有点用处-Using Verilog write serial transmission program, we hope to be of some use
new_project
- 本设计是一种基于FPGA的自动售货机控制系统设计。该设计采用FPGA作为主控，设计自动售货机控制系统。模拟实现自动售货机的货物信息存储、货物的选择与购买、金额收取、余额计算、自动找零、状态显示等功能。 采用ALTERA芯片，QUARRTUS II9.1软件，vhdl描述语言进行设计，并通过modelsim进行仿真，最终验证表明，采用FPGA设计，可以更高效，更稳定，更便捷的实现自动售货机功-This design is a vending machine control system des
2016
- VHDL有些项目可作为一个参考，水灯，串行端口，键盘，数字控制等-VHDL some projects can be used as a reference, water lights, serial port FIR, keypad, digital control and so on
SEG7_IF
- SEG7_IP.v是七段数码管的驱动程序，符合avalon总线协议，可以直接添加七段数码管的ip核使用。-SEG7_IP.v is the seven segment digital tube driver, in line with the Avalon bus protocol, you can directly add the seven segment digital tube IP nuclear use.
divider
- FPGA 循环拼接除法 循环拼接除法-FPGA Loop stitching DivisionLoop stitching Division
calculator
- simple VHDL calculator