资源列表
vga显示实验及代码
- 里面有具体的关于VGA显示的实验说明及代码，基于verilog HDL语言，里面有三个实验及代码
mcu51
- 基于IP核的51mcuFPGA程序，有顶层文件图，可以直接运行，有助于对mcu的工作原理和FPGA的理解-IP core based on the 51mcuFPGA program, there are top-level file map, can be directly run, contribute to the working principle of the MCU and FPGA understanding
P137_4_12_odd_even
- vhdl实现奇数和偶数的分频，因偶数的分频有很多历程，但奇数的分析较为繁琐，故将此结合到一起便于分析操作和分析。-VHDL to achieve the odd and even frequency, the frequency of the Division has a lot of history, but the odd number of analysis is more cumbersome, it will be combined to facilitate the analysis
example8_dianzhen
- VHDL实现点阵的操作，通过利用字模软件来得到汉字的二进制码后放到程序当中，在显示的同时数码管会相应的显示汉字所对应的字符。-VHDL implementation of the lattice operations, through the use of matrix software comes to the character of the binary code into the program in display also digital tube will display Chin
example7_jtd
- VHDL实现交通灯，通过分频操作实现对灯的控制和延时，运用的多种分频时钟来控制进程。-VHDL to achieve traffic lights, through the frequency control and the frequency of the lamp control and delay, the use of a variety of frequency control clock to control the process.
example3_counter_add_up
- vhdl语言实现对数码管的显示和对按键的控制，在对按键进行控制时可以实现连加、连减的功能显示。-VHDL language implementation of the digital display and control of the button, in the control of the button can be achieved even add, even the function of the display.
m0_array_Serial_to_parallel
- 采用m序列产生随机序列，然后通过对其进行串转并的转换输出8位，连接AD0832可以观察到噪声。-The m sequence is used to generate random sequence, and then through the serial to turn and the output of 8 bits, the connection of ad0832 can be observed in noise.
PL_MPSK
- 基于FPGA的QPSK调制解调电路设计与实现-QPSK modulation and demodulation circuit of FPGA Design and Implementation
async_to_sync_reset
- async reset to sync reset
package_crc32
- 使用VHDL语言实现crc32校验算法的程序包，其中的数据长度是32位-a package to describe crc32 based 32bits data
three_rs_255_n
- Its about Reed Solomon Decoder , in VHDL langauage
VGA_CPLD
- 基于CPLD的VGA显示设计，利用quarter软件完成功能。-VGA display based on the CPLD design, the use of quarter software to complete the function.