资源列表
Runlength-Data-Compression
- The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is
project-main-doc
- The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is
dds_generater
- 波形发生器，可以生成正弦波、三角波、方波、锯齿波；可以选择输出频率和幅度，基于DDS设计，verilog和QuartusII开发-Waveform generator can generate sine, triangle, square wave, sawtooth wave you can the output frequency and amplitude, DDS-based design, verilog and development QuartusII
src
- 基于VHDL的4*4矩阵按键识别，按键与LED相对应，每按一个按键，对应LED亮一次。-Corresponding VHDL-based 4* 4 matrix identification keys, buttons and LED, each press of a button, the corresponding LED lights up again.
SensorTemperatura
- Temperature sensor of a FPGA nexys 4 on verilog languaje
DDS
- DDS信号源实例，采用Quartus II开发环境-DDS signal source instance using Quartus II development environment
display
- vivado 7-BCD 数字显示代码。可显示4位十进制数字。输入二进制位数可自行修改。-vivado 7-BCD Digital display code。It can display four decimal digits. Enter the number of bits to modify.
clock_gyc_system
- 基于用户自定义模块的实时时钟的设计；Qsys硬件设计；-Custom real-time clock module-based design Qsys hardware design
music_player
- 基于d builder的音乐播放器的设计；FPGA与matlab联合编程；-Dsp builder based music player design FPGA and matlab joint programming
fir_filter
- 基于d builder的fir滤波器的设计；fpga高级编程-Based dspbuilder of fir filter design fpga Advanced Programming
shizhong
- 这是用VHDL编写的数字逻辑时钟电路，实现计时和由23:59到00:00转换的功能，已经在FPGA中测试通过！-This is written in VHDL digital logic circuit。It can realize the function of timing and by 23:59 to 00:00 conversion, has been in the FPGA test through!
ad_spi
- AD2548 SPI读写时序 VHDL-AD2548 SPI