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  1. Log2_calc

    0下载:
  2. Log2 calculator used for audio level measure
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:1.02kb
    • 提供者:ahmad
  1. Black_frezz_det

    0下载:
  2. Detestor of Black and Freeze in live video-Detestor of Black and Freeze in live video
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:1.36kb
    • 提供者:ahmad
  1. Keyer

    0下载:
  2. Video Keyer supporting Luminance key, Self key, Matt key and Split key
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:1.49kb
    • 提供者:ahmad
  1. Wipe

    0下载:
  2. Rectangular wipe generator
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:1.47kb
    • 提供者:ahmad
  1. Video_mixer

    0下载:
  2. Video transient with support of Fade, Wipe, Cut and Fade to black.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:2.29kb
    • 提供者:ahmad
  1. ethernet

    0下载:
  2. 在xilinx用verilog实现工业以太网的全部文件-industrial ethernet in xilinx
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-14
    • 文件大小:3.22mb
    • 提供者:姜智
  1. MAC

    0下载:
  2. 用verilog实现MAC控制器的各个模块详细代码-mac controller
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-30
    • 文件大小:17.18kb
    • 提供者:姜智
  1. arctan-Function-Approximation

    0下载:
  2. If we implement the arctan(x) using the embedded 9 × 9 bit multipliers we have to take into account that our values are in the range − 1 ≤ x < 1. We therefore use a fractional integer representation in a 1.8 format.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:312.82kb
    • 提供者:hooman hematkhah
  1. Circular-CORDIC-in-Vectoring-Mode

    0下载:
  2. The first iteration rotates the vectors the second or third quadrant to the first or fourth, respectively. The shift sequence is 0,0,1, and 2. The rotation angle of the first four steps becomes: arctan(∞) = 90◦ , arctan(20) = 45◦ , arctan(2
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-01
    • 文件大小:274.18kb
    • 提供者:hooman hematkhah
  1. Anderson--Algorithm

    0下载:
  2. We assume that denominator and numerator are normalized as, for instance, typical for floating-point mantissa values, to the interval 1 ≤ N, D < 2. This normalization step may require essential addition resources (leading-zero detection and two ba
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-30
    • 文件大小:194.12kb
    • 提供者:hooman hematkhah
  1. 8-bit-Restoring-Divider

    0下载:
  2. Division is performed in four stages. After reset, the 8-bit numerator is “loaded” in the remainder register, the 6-bit denominator is loaded and aligned (by 2N− 1 for a N bit numerator), and the quotient register is set to zero. In the second a
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-01
    • 文件大小:223.75kb
    • 提供者:hooman hematkhah
  1. I2C

    0下载:
  2. 能够完整实现I2C,有详细的代码注释,非常容易理解。-Can fully realize the I2C, a detailed code notes, very easy to understand.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-24
    • 文件大小:6.86mb
    • 提供者:glywhh
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