资源列表
apb
- These are the files of apb verification environment. Some of them are useful as a reference for creating the other verification environment.
Camera_Logic
- 双目视觉成像，双目视觉摄像头，3D摄像头对应的FPGA图像采集逻辑程序。1> 适用于：单目和多目视觉系统。2> 附图为双摄像头系统，应用了两条图像控制流水，源码对应图中红色的逻辑块，本人已实测代码为OK。-Imaging binocular vision, binocular vision camera, 3D camera image acquisition corresponding FPGA logic program. Applies to: monocular vision
AS-SSD-Benchmark
- this APP likes shit do you like you can eatand happy go fucking it -this APP likes shit do you like you can eatand happy go fucking it
StateMachine
- VERILOG语言，ISE13.4实现的步进电梯的状态机，可以仿真。-VERILOG language, ISE13.4 achieve step elevator state machine can be simulated.
KEBIANCHENGLUOJIQIJIANPEIXUN
- 参加电子设计大赛不可或缺的可编程逻辑器件的系统培训资料-System training materials to participate in Electronic Design Contest integral programmable logic devices
rs232_auto
- verilog实现通过RS232自发自收，波特率为115200，传输格式为1位起始位，8位数据位，1位停止位，无校验位-verilog through RS232 spontaneous self-closing, 115200 baud rate, transmission format is one start bit, 8 data bits, 1 stop bit, no parity bit。
LTC_1867_driver
- Verilog实现LTC1867的驱动程序，功能：四路单端输入CH0~CH3，系统时钟频率50MHZ，SCK为12.5MHZ，接收数据按通道四路实时输出，输出频率为100HZ，16位数据。-Verilog realize LTC1867 driver features: four single-ended input CH0 ~ CH3, the system clock frequency is 50MHZ, SCK is 12.5MHZ, receive data by channel fo
UART
- UART串口接受发送，串口调试助手与nexys3进行通信-UART serial ports that accept transmissions
UART
- 在DE2开发板上实现串口收发设计，系统时钟频率为50MHz,reset信号低电平有效，输入数据最高位为1时按位取反再输出-Achieve serial transceiver design DE2 board, the system clock frequency of 50MHz, reset active low signal, the input data is the most significant bit is 1. Bitwise re-export Google 翻译（企业版
Mouse2
- mouse led program module VHDL
YD
- 运用qurtus9.0进行全数字锁相环的制作，内含有各个模块及程序注释。-Of all digital phase-locked loop with qurtus9.0 production, contains various modules and application notes
yejinxianshipin
- 液晶显示屏（LCD）用于数字型钟表和许多便携式计算机的一种显示器类型。-Liquid crystal display screen (LCD) used for digital clock and a display type of many portable computer.