资源列表
spi_rtl
- spi的rtl级代码设计，内含spi_slave和spi_master的行为模型-Rtl level behavioral model of spi code design, and includes spi_slave of spi_master
CrossClockDomain
- 跨时钟域设计不错的设计，进过modelsim仿真通过。-Cross-clock domain design is good design been to modelsim simulation through.
ddr
- ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
filtra-lowpass
- this a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR-this is a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR
ahb_bus
- ahb总线代码,现支持4个master，可扩展-ahb bus verilog module
ASI_simulation
- 异步串行接口ASI仿真设计,quartus modelsim 仿真参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI simulation design, quartus modelsim simulation reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
ASI
- 异步串行接口ASI,QUARTUS cv demo参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI, QUARTUS cv demo reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
timing_constraint
- 三速以太网时序约束参考设计，内涵quartus ii 工程，sdc文件-Triple-Speed Ethernet reference design timing constraints, content quartus ii project, sdc file
ddr2
- ddr2 仿真模型，适应于modelsim 仿真，内涵仿真核源码-ddr2 simulation model adapted to the modelsim simulation, simulation connotation nuclear source
lms_adaptive_filter.vhd
- lms adaptive filter using desired and input stream to get the output with 4 tabs filter.
Quartus_II_12.0PQsys_Nios_II
- 特权同学经典教程，《Quartus_II_12.0+Qsys及Nios_II教程》,需要的同学赶快来下载吧。-Privileged students Tutorial classic, Quartus II 12.0+ Qsys and Nios II Course , students need to hurry to download it.
ax516_20150304A
- 黑金ax516开发板原理图20150304A，需要的同学赶快来下吧。-Black Gold ax516 development board schematics 20150304A, students need to hurry to the next bar.