资源列表
Ripple-carry-adder
- Ripple carry adder using system verilog
24T
- 24小时周期时钟设计，通过quartus模块实现24小时周期时钟，包含模拟的时钟脉冲。-24 hour cycle clock design, through the quartus module to achieve a 24 hour cycle of the clock, including analog clock pulse.
fft_core_test
- 基于FPGA的FFT的IP核实现，有其详细源码，采用verilog语言编写，内容详细-The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content
wenduji
- 基于FPGA的温度计设计。感温原件测量环境温度并显示在七段数码管上，可选择华氏温度或摄氏温度显示，超过预设温度有提示音，超过温度上限后会发出警报。- FPGA-based design of the thermometer. Original ambient temperature measured and displayed on the seven-segment LED, selectable Fahrenheit or Celsius temperature display, tem
musicplayer
- 基于FPGA的音乐播放器设计。能播放3首乐曲，播放过程可随时暂停或续播，可调C调与G调，音量可控制，可手动切换歌曲。-FPGA music player based on. Can play three songs during playback to pause or resume playback, adjustable C and G tune tone, volume can be controlled manually switch songs.
12_24clock
- 基于FPGA的数字万年历设计。可显示年月日时分秒星期，可校时，可整点报时。-FPGA-based design of digital calendar. Displays the date when the minutes and seconds the week, when the school can be the whole point timekeeping.
kb
- 基于niosII系统的PS2键盘测试程序，测试PS2键盘与niosII内核的通信是否成功。该程序在Quartus自带的eclipes下编译运行。-Based nios II system PS2 keyboard test procedures, test PS2 keyboard and niosII kernel communication is successful. Compile and run under Quartus comes eclipes.
traffic
- traffic vhdl code -traffic vhdl code ......
digital-clock
- Digital clock vhdl code
alu1
- VHDL Code for ALU -VHDL Code for ALU .......
temp
- temprature converter VHDL code
CLA_4
- 用verilog语言编写的CLA_4文件。CLA_4是4位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 4 files. CLA 4 is a four-ahead adder source code after the code verification function correctly, readers can write their own testbench code for ver