资源列表
SPconversion_CPLD_FPGA_VHDL
- 基于状态机的8bit并串变换，使用VHDL语言，使用Xilinx ISE，程序特点是使用了状态机，通过分析可以学习如何使用状态机编程，并完成8bit并串变换的功能-8bit based on state machines and string transformation, using VHDL language, using the Xilinx ISE, process characterized by the use of the state machine, the analysis c
irdaGET
- 红外通讯接收，irda通讯接收，红外通讯测试-Infrared communications received, irda communications received infrared communication test
watch
- 电子时钟 由8个数码管显示12小时制的时间
frequence
- VHDL语言频率计的设计，分为三个模块，计数模块和16位寄存器模块还有时序控制模块。-VHDL, the design of frequency meter
lab2
- 使用chdl 实现音谱转换的小实验，可以作为音乐翻译的样子-Convert audio spectrum using chdl achieve a small experiment, translated as the way music
FIFO
- 用VHDL语言编程实现的FIFO的设计，可用于数据的寄存和缓冲，libero仿真通过-Programming language using the FIFO VHDL design can be used for data storage and buffering, libero simulation by
Hamming32
- It has a simple verilog code to calculate 32 bit hamming distance and a test bench to simulate.
state
- 简单状态机数码管显示,Quartus II VHDL设计语言-Asimple state machine digital tube display, Quartus II VHDL design language
watch_dog
- 看门狗程序设计，使用verilog HDL语言编写-Watchdog program design, using verilog HDL language
sdmrbeh
- This code implements the behavioral modelling of a Moore type sequence detector to detect the sequence 1010. The code is a quartus project file
DCM_12M_1M
- xilinx下DCM输出12Mhz和1Mhz-Verilog DCM xilinx ISE
frequent
- FPGA等精度测频模块，实现任意频率的等精度测量-FPGA and other precision frequency measurement module, such as precision measurement of any frequency