资源列表
even_odd
- VHDL实现的奇偶校验功能模块和一个外设配置寄存器的设计实例。
FixToFloat.将16位二进制有符号纯小数转换为32位单精度浮点数
- 将16位二进制有符号纯小数转换为32位单精度浮点数。实际应用时，最好加tsu、tco约束条件，速度会快些。,There will be 16-bit binary decimal symbol is converted to pure 32-bit single precision floating point. Practical applications, it is best to increase tsu, tco constraints, the speed will be faste
fuzzy_inanalyser
- VHDL模糊PID控制控制器模糊化程序。-Fuzzy PID control of VHDL programming fuzzy controller.
ram_sp_ar_aw
- VHDL源代码,资源多多共享,不懂的地方多多指教
sdmlbeh
- This code implements the behavioral modelling of mealy type sequence detector to detect the sequence 1010. The code is a quartus project file.
alu
- This arithmetic logic unit accepts 8-bit inputs, but it can easily be modded to higher bits. It supports the addition, subtraction, set if less than, AND, and OR operations. The operation to perform is determined by the 3-bit address bus.
FPGA_LCD_VerilogCode
- 利用Verilog语言编写的LCD控制代码，在LCD上显示信息-Using Verilog code written in LCD control, display information on the LCD
vhdlchufaqi
- 这是一个基于VHDL语言的bch除法器，其功能就是实现二进制除法，采用移位的方式进行-This is based on VHDL language bch divider, its function is to achieve binary division, the way by shift
LED
- 实现LED灯的渐变显示和静态亮度不同的静态显示。-Gradient of LED lights and static display of a static display of different brightness.
as_fifo1
- 实现异步FIFO功能，实现串行数据通讯功能，可以用FPGA实现串口扩展-Asynchronous FIFO functions, serial data communication
weisuiji
- 实现f(x)=1+x^4+x^9的伪随机序列发生器-Pseudo-random Sequence