资源列表
pwm_gen
- PWM _Generator VHDL code
FIR_cautruc_truc_tiep
- this is FIR filter by VHDL
Bus_REG_Clk_Crosser
- Clock crosser of register bus
fenpin
- 实现了1到62553的任意分频，且文件中包含测试文件，是个不错的选择。-1-62553 any divide the file containing the test file, is a good choice.
butterfly
- 蝶形运算的VHDL代码，可以实现，没验证-VHDL code butterfly operations can be achieved, no authentication
sdmlstruct
- This code implements the structural modelling of mealy type sequence detector to detect the sequence 1010. The code is a quartus project file
DDS
- 同时用verilog 语言编写dds原代码用于生成正余弦波，并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
vlsiram
- VHDL RAM 16 * 8 source code FPGA
gcd
- 求最大公约数的vhdl 源代码 gcd-gcd
dpll
- dpll is used to lock the data
clk
- 这是一个数字秒表的设计。几时周期为0.01s-1h。带有计数器的清零端，还有一个秒表的计时起止控制开关，最后计时信息显示在数码管上。-This is a digital stopwatch design. When a period of 0.01s-1h. Cleared with the end of the counter, and a stopwatch start and end time-control switch, the last time the information di
PWM
- PWMc语言代码，产生PWM波形，用于各种产品以及测试-PWMc language code to generate PWM waveforms for a variety of products and test