资源列表
prbs
- 伪二进制随机码的产生，在fpga上已经验证-Pseudo-random binary code generation
fifo
- 同步fifo，使用ISE13.4 V5器件 速度550MHz-Synchronous fifo, use ISE13.4 V5 device speed 550MHz
checkNodee_Behavioral_VHDL
- LDPC码校验节点（checknode）进行奇偶校验方程时的vhdl编程，硬件语言实现-LDPC check nodes (checknode) carried out at the time of parity equation VHDL programming, hardware language
StateMachine
- 典型的状态机，简单的状态机可以不需要编码，也可以采用one-hot编码方式，如果状态很多时，采用格雷码，能有效避免亚稳态。-A typical state machine, a simple state machine can do without coding, can also be used one-hot encoding, if the state in many cases, the use of Gray code, can effectively avoid metastable
cymomete
- 采用测频法设计一个8位十进制数字显示的数字频率计。测量范围1-499999hz。-Frequency measurement method used to design an 8-bit decimal figures show that the digital frequency meter. Measuring range 1-499999hz.
sdmrstruct
- This code implements the structural modelling of mealy type sequence detector to detect the sequence 1010. The code is a quartus project file
VGA
- VGA显示控制模块VHDL描述，行场计数器地址接入R、G、B信号端可以显示彩条-VHDL descr iption of VGA display and control module
AD_R
- AD7685芯片采集程序，可以自行设置采样率，经检验可用。-The AD7685 chip collection procedures, available.
zuoyepaoma2
- 基于FPGA的跑马灯设计，可实现一个灯独跑，两个灯连跑，间断跑，隔着2个灯跑自定义跑灯形式。quartus软件亲测可用，自己编写的~-Marquee FPGA-based design can achieve an independent running lights, two lights Lianpao, intermittent run, run across two lights running lights in the form of custom. quartus software
divider
- 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率 事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value o
recovery
- 恢复时钟信号的代码,用于数字通信中，used to recovery the timing from data-used to recovery the timing from data
tmx
- 采用了FPGA编程，学习LCD，实现了LCD显示频率计的功能。-FPGA programming, learning the LCD, the LCD display the frequency meter.