资源列表
Quartus
- Quartus的鉴相器硬件电路设计 Quartus的鉴相器硬件电路设计 -Quartus the hardware design phase detector phase Quartus' s Quartus hardware circuit design of hardware circuit design phase
411
- XILINX V5的库文件和开发指导文档-XILINX V5 libraries and development guidance document
BCH_EN
- 基于FPGA的GPS/BD信号发生器中BCH编码发生器模块，使用verilog编写- FPGA-based GPS/BD signal generator BCH code generator module, using verilog write
RISC_cpu
- 一款8位的RISC-cpu 源码可在modelsim仿真出波形-An 8-bit RISC-cpu source code in modelsim simulation waveforms
Experiment04
- 浮点数的除法器的Verilog 源代码，使用Quartus II开发环境编写，塞琳思的ISE可能打不开-floating-divider s Verilog codes,can be opened by Quartus and not by ISE
数字信号处理的FPGA实现-第三版-verilog源程序
- 数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
Dpsk
- 基于数字接收机，DSPK解调技术的FPGA实现，是一个完整的工程，非常有利于学习。-Based on the digital receiver, DSPK demodulation technology of FPGA implementation, is a complete project, very conducive to learning.
AN119
- AMBA Application Note: AN119 - AHB masters and slaves design for Virtex 2 Logic Tile. -AMBA Application Note: AN119- AHB masters and slaves design for Virtex 2 Logic Tile.
Edition
- VHDL可重用英文书,书中有许多对VHDL可重用的具体介绍,是一般的相关书籍所没有的.
Reuse-Methodology-Manual-Third-Edition
- 进行SOC/IP 设计以及可重用设计的宝典书籍！是synopsys的一位牛牛写的！ 主要以mentor和synopssy的设计工具为流程，讲述了SOC/IP可重用设计，验证设计的基本方法。 -For SOC/IP design and reusable design book books! A synopsys Niuniu is written! To mentor and synopssy the main design tools for the process, about the
i2c_master_slave_core_latest.tar
- IIC IP核，可以直接集成在SOPC中的(⊙o⊙)哦-基于Quartus II 可直接集成到SOPC，自定义II C IP核
i2c_master_slave_core_latest.tar
- This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave. VMM Test-bench is also available.