资源列表
CPLDVHDLCODE
- CPLD VHDL CODE非常好的参考资料-CPLD VHDL CODE a very good reference
VHDL_Development_Board_Sources
- 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development
Avalon
- Avalon总线规范的简单介绍
emi_ip
- External Memory Interface Handbook
hanshufashengqi
- 设计一个函数发生器，用VHDL语言实现。可以实现正弦、余弦等多种函数的波形-Design a function generator using VHDL. You can achieve a variety of functions such as sine, cosine waveform
DDS
- DDS直接数字合成器，里面包含相关的顶层文件，加法器，D触发器，mif文件(DDS direct digital synthesizer, which contains related top layer files, adder, D trigger, MIF file)
axi_lite_user
- axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)
DDSVHDLCODE
- 本人收集的多个VHDL语言编写的正弦波发生器以及SPWM程序。-I collected multiple VHDL language of sine wave generator SPWM program.
Mars-EP1C6-F_code2
- 此包为FPGA学习板接口实验程序源代码,共包括13个实验程序,有7段数码管,1602液晶显示,12864液晶显示,I2C总线,串口通信,拨码开关等.-The packet interface to FPGA board experimental procedure to study the source code, a total of 13 experimental procedure, there are 7-segment digital tube, 1602 LCD 12864 LCD,
pcie_ml555x4_prj
- 4通道pcie设计,实际应用中需要，不过需要自己修改相关部分-4 channel pcie Design
Verilog_Helper
- 一个简单的verilog绘图工具，工具向数据库导入电路连接信息，程序通过数据库的信息刷新屏幕，并且向用户导出门级建模的verilog语句-Verilog a simple drawing tools, tools, electrical connections to the database information into the program information through the database to refresh the screen, and exported to th
FPGA_5
- 无SDRAM的PCI采集,给出PCI采集的FPGA程序，桥芯片也为PLX9054，已验证通过-No SDRAM, PCI capture, given FPGA PCI acquisition program, bridge chips for PLX9054, has been verified by