资源列表
(Kluwer)-Verilog-Quickstart--Practical-Guide-to-S
- A Practical Guide to Simulation and Synthesis in Verilog. Third Edition
PPT_Tutorial_ETH
- 瑞士苏黎世大学VHDL课件.对入门初学者有一定帮助。-University of Zurich, Switzerland, VHDL courseware. Of entry to some extent help the beginners.
Verilog_Quickstart
- James M. Lee 的大作，学verilog必备图书-verilog quick start
RS2
- 该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间-The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this
lcd5110_耗费资源少
- Quartus II 项目，可驱动LCD5110液晶显示屏。(This zip file contains a quartus ii project, which can driven the LED screen LCD5110.)
clocksystem
- 本文件是针对了解闹钟控制系统而写的一个VHDL源代码。-This document is aimed at understanding clock control system and write a VHDL source code.
DA_fir
- 基于分布式算法的FIR滤波器设计及FPGA实现-Distributed algorithm based on FIR filter design and FPGA realization of
Based-on-FPGA-of-FIR-filters
- 基于FPGA的高阶FIR滤波器的设计，数字滤波器，分布式算法，CSD编码-Based on FPGA order FIR filters
USB20D
- USB20D模块数据传输控制程序，包括FIFO的运用和数据上传下载-USB20D model translation
OpenBTS-USRP1
- 用于OpenBTS USRP1 Cyclone FPGA比特流的Altera Quartus项目-Altera Quartus Project for OpenBTS USRP1 Cyclone FPGA bitstream
68013
- 使用68013的测试程序，包含68013固件程序-use of cy7c68013,data transfer from usb to pc.
20180125_5M_01
- 基于verilog产生伪随机二进制序列，序列速率为5M(A pseudo-random binary sequence based on verilog.)