资源列表
WorkOneBetaC
- 低频数字相位测量仪 Verilog源代码 经过实测可用 信号频率20Hz-20KHz，步进20Hz 幅值0-5V，步进40mV。-Verilog code Through the measured signal frequency available 20 hz- 20 KHZ, step 20 hz Amplitude 0 to 5 v, stepping 40 mv.
Digital-storage-oscilloscope
- 电赛 练习题目 数字存储示波器 FPGA实现-The CECW practice the subject of digital storage oscilloscope FPGA implementation
add xilinx embeded ip
- add xilinx embeded ip
lab3_adding_ip
- xilinx embeded添加ip的源程序,包括工程文件-xilinx embeded adding ip
Virtex5user-guide
- VIRTEX用户文档，非常适合初学者和学习xilinx原语的同志学习-VIRTEX development must the Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
TLC1650
- TLC1650驱动程序 Verilog HDL-TLC1650driver Verilog HDL
cpu
- 这是本人的课程设计。采用微程序控制的CPU，能够从RAM中读取指令，并执行。包含MBR,MAR,IR,BR,ALU,PC等功能部件，能实现加减乘法，逻辑左右移位，逻辑与或非，在此基础上还可以拓展。希望能帮助你们。-This is my curriculum design. Micro-program control CPU can read instructions from the RAM and executed. Contains the MBR, MAR, IR, BR, ALU, PC
SPWM-output
- 利用FPGA，采用DDS技术产生具有死区控制的SPWM波-To utilize FPGA, generation of DDS technology with deadband control SPWM wave
Test_final_ver1.01
- VHDL code for IFFT8pts Have fun!
MySD_Card
- verilog 语言，介绍在niosII下的SD卡读写。-verilog language
verilog100
- 一百多个例子很好的verilog 学习资料，大家可以多多参考，适合初学者学习
aes3_rev1.0
- AES3在altera FPGA上开发的参考案例-AES3 Reference Design v1.0 The AES3/EBU reference design provides both a transmitter and a receiver. The receiver extracts the data and the clock an incoming AES3/EBU stream and stores the parallel audio data and