资源列表
flash
- 通过NIOS环境用C语言对Flash进行读写操作，对初学者有很好的参考价值 -NIOS environment by using C language on the Flash read and write operations on the value of a good reference for beginners
ddpi_rx
- 描写处理器与FPGA之间的接口程序，使用verilog语言编写-Describes the interface between the processor and the FPGA program, using the verilog language
traffic
- 采用 EDA 技术，并应用目前广泛应用的VHDL 硬件电路描述语言，实现交通灯系统控制 器的设计。掌握使用VHDL 语言设计有限状态机的方法。-Using EDA, and applied widely applied to the VHDL language, hardware circuit to describe traffic control system Design. Master use VHDL language design method of finite state
sign_by_unsign_multiplication
- sign by unsign and sign by sign multiplication in verilog
full_add
- 全加器，可移植性很强，只需要变换一下里面的数字就能得到任意的全加器！-The counter, portability is very strong, only need to a change in the inside of the digital can get any counter!!!!!
rtl
- led and 7segment with verilog
sram_vhdl
- 基于vhdl的sram读写访问程序，经过前后仿真及板上实际测试-failed to translate
CM_WADDR
- Complex multiplier with twiddle factor
ZIDONGDIANTIKONGZHI
- 三层的电梯控制,具备显示，加速，以及开关门的延时等操作-Three elevator control, including a display, acceleration, and an operation switch gate delay and other
VHDL-8bitFIFO
- FIFO的宽度：也就是英文资料里常看到的THE WIDTH，它只的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等，本程序实现8位的FIFO功能,三位格雷码可表示8位的深度。-THE WIDTH of THE FIFO: namely information in English often see THE WIDTH, it is only a FIFO data read and write operations, as has 8 bit or 16 bit M
H bridge CPLD driver
- Verilog H bridge driver with a Enable control
trd106s
- CPLD H bridge driver