资源列表
Frequency_Divider_VhdlCode
- a very good frequency divider code for fpgas>
fir
- Verilog编的fir滤波器，可以自己输入参数序列，产生滤波波形-Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
counter
- 计数器整体的功能为完成计数定时（00：00—59:59:99），要完成1个小时的计数范围-The overall function of the counter from time to time for the completion of counting (00:00-59:59:99), to complete the count range of 1 hour
gen_ecc
- ecc generator Error Correction Coding -ecc generator Error Correction Coding
4_4keyboardscan
- 4*4键盘扫描程序,基于viretex-4开发平台-4*4 keyboard scan ,which is based on the viretex-4 serial .There are many function pin .you must identificate them
KeyboardController
- keyboard controller for spartan 3e fpga
watch2
- vhdl实现watchdog，在逻辑中可以加入本模块，实现看门狗。-VHDL achieve watchdog, the logic of the modules can be added to achieve watchdog.
CHENGXU
- 8253定时期的实现。。只介绍方式的代码程序
veriloghdlcsdm
- 用verilog hdl 硬件描述语言写的一个范例程序，led的，扩展性极强，欢迎大家下载使用。-Verilog hdl using hardware descr iption language to write an example of the procedure, led, and highly scalable, welcome to download.
detseq
- verilog 序列检测器实例，检查输入数据中某一种序列是否出现-verilog sequence detector instance, check the input data, whether there is a particular sequence
fr_regen
- 完成帧头的跨时钟处理，以减少信号的非周期性抖动等。-fr process
fifo数据缓冲器的vhdl源程序
- 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8 * 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges