资源列表
clock_monitor
- 时钟监测模块，在系统运行过程中，时刻保持对时钟频率的检测-Clock detection module, the system is running, keep the clock frequency detection
vga
- This VHDL sample demonstrates how to generate a VGA signal to make it possible to connect an FPGA to a monitor. Written for Mimas v2, but probably easily adapted to any other board with a VGA connector on it (that can also be done by manually connect
yuandengke
- 袁登科的永磁同步电机一书书，里面的全部源代码，-yuandengke pmsm of book matalb
151019_halfadder
- 此程序是FPGA 中用VHDL语言来实现半加器的功能，对于初学者很有参考价值。-This program is FPGA using VHDL language to achieve a half-adder function, a good reference for beginners.
mipsx2
- 基于FPGA的SOC设计与功能测试，利用mips指令集编写的soc片上系统，以及功能验证- SOC design and FPGA-based functional test, use mips instruction set written soc system on a chip, and functional verification
sine_package
- ve verilog va tai lieu
verilog
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
frequence_430new
- 基于FPGA的数字频率计的设计，可测量波形的频率周期占空比等-Digital frequency meter design FPGA-based, measurable frequency waveform cycle duty cycle
spi
- spi 驱动Verilog代码 可以配置任意模式长度，时钟最高支持50M（再高没有测试过）-spi driver
CRC32_D64
- 10G以太网，64b比特CRC32计算,10G以太网，64b比特CRC32计算-CRC32 with 64 bits in 10G Ethernet
201604plj
- 利用FPGA测试信号的频率，利用内部高速计数器和等精度测量方法，实现对外部信号的精确测频。测量范围10Hz~100M。-FPGA using the frequency of the test signal, and using the internal high-speed counters and other precision measurement method for accurate measurement of the frequency of the external signa
sdi_nrzi_enc
- BT1120格式的NRZI编码,并行算法-NRZI encoding BT1120 format, parallel algorithm