资源列表
floating-point-multip
- verilog code for floating point multiplier
fibonaccicode
- verilog code for fibonacci codes
bus-invertcoding
- verilog code for bus invert coding
cgra-full
- verilog code for cgra architecture
can-sja1000
- CAN总线开发代码，FPGA与sja1000通信，可实现CAN的接收和发送。-The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.
chuzuche
- 出租车vhdl程序，并带有testbench仿真程序，通过开始按键复位，然后根据行使信号进行公里计数，起步价3公里8元钱，超过3公里一公里1元钱-Taxi vhdl program, with a testbench simulation program, started by the reset button, then the exercise kilometer count signal, starting at 3 km 8 yuan, more than three kilometer
Stopwatch
- 在quatus平台，verilog语言编写的秒表代码。实现功能开始，暂停，复位，显示暂停。在Cyclone2上运行通过。-In quatus platform, verilog language stopwatch code. Achieve functional start, pause, reset, pause the display. On Cyclone2 run through.
PS2shubiao
- 基于FPGA的PS2鼠标项目 EP4CE系列-PS2 mouse project based on FPGA
CD1_MT9M034_DISPLAY_SAVE
- 基于FPGA的MT9M034图像采集显示并存在TF卡是的例程，FPGA和SDRAM完成了RAW图像的采集和转成RGB，并通过VGA显示。NIOS完成了RGB图像存成BMP图像的功能和CMOS的IIC配置-Based on FPGA MT9M034 image acquisition and displayed and TF card is routines, FPGA and SDRAM completed the acquisition of raw image and convert the
CD1_MT9V034_RAW_TRANS
- 基于FPGA的UDP网络图像传输实验，FPGA完成了MT9V034的RAW图像采集缓存，NIOS完成了图像的UDP封包，DM9000芯片完成了MAC和PHY的功能。-Based on the UDP FPGA network image transmission experiment, FPGA completed the RAW MT9V034 image acquisition cache, NIOS completed the image of the UDP packets, DM900
CD1_PHOTO_ABLUM_1920
- 使用FPGA做的数码相册实验，用NIOS做了FAT32文件系统和JPEG图像解码,FPGA和SDRAM做了显示的缓存-Using FPGA to do the digital album experiment, using NIOS to do the FAT32 file system and JPEG image decoding, FPGA and SDRAM to do the display cache
CD1_PHOTO_ABLUM_1280
- 基于FPGA的数码像册实验，使用了NIOS做文件系统和JPEG图像解码FPGA和SDRAM做了图像缓存-Based on the FPGA digital image book experiment, using the NIOS to do file system and JPEG image decoding FPGA and SDRAM do the image cache