资源列表
HDLC_FPGA
- HDLC接口协议的FPGA实现,使用Verilog hdl-FPGA HDLC interface protocol implementation using Verilog hdl
highspeed_96
- 高速数传QDPSK调制程序，V4板子可以用-High-speed data transmission QDPSK modulation process, V4 board can be used
reg
- 8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out- 8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out
vhdl_CRC_generatir
- CRC 產生器，VHDL 語言， 適合 FPGA 練習使用-CRC generator , VHDL language, Good for FPGA learnning
mt46v16m16p_ddr
- 官网下载的，经过板级验证的ddr control mt45v16m16p源代码，verilog语言设计，希望可以用到系统化设计。-Official website to download, through board-level verification ddr control mt45v16m16p source code, verilog language design, hoping to use systematic design.
slavefifo
- FPGA 3D camera experiment
7seg
- 7seg.rar this file is use to fpga(altera) HEX-7seg verilog/VHDL-
uart_back
- 串口回传verilog源代码 uart back code verilog-uart back code verilog
uart
- 串口verilog源代码 uart code verilog-uart code verilog
display_sm
- 数码管扫描verilog源代码 display code verilog-display code
buzzer_sos
- 蜂鸣器源代码buzzer code verilog-buzzer code verilog
breath_led
- verilog breath led sourece code