资源列表
CLA_20
- 用verilog语言编写的CLA_20文件。CLA_20是20位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 20 files. CLA 20 is 20 lookahead adder source code after the code verification function correctly, readers can write their own testbench code fo
FSM
- 用verilog语言编写的FSM文件，有限个状态及在这些状态之间的转移和动作等行为的数学模型，在计算机领域有着广泛的应用。-Mathematical model with verilog language FSM file transfer and finite number of states and actions between these states and other behavior in the computer industry has a wide range of appl
FIFO
- 用verilog语言编写的FIFO文件，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令，希望能够帮助读者-With verilog language FIFO file, which is a traditional sequential execution method, first enter the command to finish and retire, followed by only the second instruction execution, h
xapp223
- UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buffer for Virtex, Virtex-E and Spartan-II FPGAs-UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buf
xapp345_verilog
- Synthesizable Verilog UART source code.
DS18B20
- DS20B18温度采集模块（一线式总线读取）-DS20B18 temperature acquisition module (bus line read)
SDRAM
- 基于FPGA的nios ii嵌入式SDRAM应用开发程序，仅供参考学习使用，谢谢。-NIOS based on the II FPGA embedded SDRAM application development process, only reference learning to use, thank you.
RTC
- 基于FPGA的nios ii嵌入式RTC应用开发程序，仅供参考学习使用，谢谢。-NIOS based on the II FPGA embedded RTC application development process, only reference learning to use, thank you.
LED
- 基于FPGA的nios ii嵌入式LED应用开发程序，仅供参考学习使用，谢谢。-NIOS based on the II FPGA embedded LED application development process, only reference learning to use, thank you.
INT
- 基于FPGA的nios ii嵌入式中断应用开发程序，仅供参考学习使用，谢谢。-NIOS based on the II FPGA embedded interrupt application development process, only for reference learning to use, thank you.
ICC
- 基于FPGA的nios ii嵌入式ICC应用开发程序，仅供参考学习使用，-NIOS based on the II FPGA embedded ICC application development process, only reference learning to use, thank you.
ADC0804
- 基于adc0804lcn的verilog 程序转换，程序提供了一个范例，仅供大家学习参考-Adc0804lcn based on the Verilog program conversion, the program provides a sample, for everyone to learn the reference