资源列表
pinlvji-design-VHDL
- 使用Altera公司的EP2C35系列的FPGA芯片，利用SOPC-NIOSII-EP2C35开发板设计和仿真一个数字频率计，对1Hz~250KHz 的脉冲进行频率测量，采用等精度测量，即在所测量的整个频段内部，均可实现相同精度的测量，测量精度与频率无关，结果在数码管上显示-The use of Altera EP2C35 series FPGA chip using the SOPC-NIOSII-EP2C35 board design and simulation of a digital
liushuideng
- 流水灯，控制方向，对系统时钟进行分频，奇偶数闪亮-Water lights, control direction, the system clock frequency, odd even flashing
GTX4
- 光纤发送接收模块，verilog编写，主要用于光纤的发送和接收，波长1310nm-Fiber optic transmitter receiver module, verilog written primarily for transmitting and receiving the optical fiber, wavelength 1310nm
DE2_115_pin_assignments
- de2-115引脚的配置，quartusII的设置-de2-115 configuration pins, quartusII settings
DE2-115_labs_vhdl
- DE2-115板上的，lab-exercise的PDF历程-, Lab-exercise of PDF course DE2-115 board
DE2-115_labs_verilog
- PDF格式的Verilog，DE2-115板的历程-PDF format Verilog, DE2-115 plate course
yiweijicunqi
- 移位寄存器的原理图设计，基于quartusII软件。-Shift register schematic design, based quartusII software.
shuzipaobiao_all
- VErilog源码，数字跑表数码管显示，按键控制-VErilog source, digital stopwatch digital display, control buttons
source
- FPGA串口，verilog HDL串口收发程序-FPGA serial, verilog HDL serial transceiver procedures
write
- 使用golang生成一个coe文件，初始化rom。其中随机产生10000个数值作为初始化值-Use golang generate a coe file to initialize rom. Wherein the randomly generated value as the initial value 10000
state_led_one
- 基于verilog HDL的状态机8位流水灯（一个按键控制左转和右转），开发环境Diamond 3.7(64-bit)；FPGA采用LCMXO2-1200HC-4MG132C；时钟25M；开发板：与非网小脚丫-Based verilog HDL state machine eight light water (a key control buttons turn left and turn right), the development environment Diamond 3.7 (64-b
Sequential-Multiplier
- sequential multiplier using system verilog