资源列表
qpsk
- QPSK调制程序的testbench程序 timescale 1ns/1ns //单位时间，时间精度 module qpsk_tb //qpsk调制的testbench reg clk reg rst reg x wire y -QPSK modulation program testbench program timescale 1ns/1ns // unit of time, time accuracy module qpsk_tb // qps
pwm
- 使用VHDL实现可调的PWM控制器，便于初学者学习-Use VHDL to achieve an adjustable PWM controller, easy for beginners to learn
SDRAM
- sdram 状态机驱动源程序工程 完全使用verilog hdl写的-sdram state machine driver source project written entirely in verilog hdl
pro
- S10420背照式CCD verilog 状态机驱动代码-S10420 back-illuminated CCD verilog state machine driver code
hex-2-led
- 基于VHDL的数码管点亮实验，针对DE2开发板-Digital tube experiments based on VHDL for DE2 board
VGA-code
- 基于verilog 的vga设计，有多种分辨率可供选择-the design of vga driven based on Verilog。it s a variety of resolutions to choose
freq_divide_100
- 基于VHDL的分频计数设计,针对ED2开发板分配引脚-Frequency count based on VHDL
9826
- 针对AD9826驱动设计的Verilog代码，主要是配置ccd采样的设计-The Verilog code is designed for AD9826, to configuration ccd sampling
22269
- 大量的FPGAverilog语言示例源码，可以-A lot of language FPGAverilog example source code, can take a look
altera_1c12_test
- 基于FPGA的串行flash读写设计程序源码-Based on the FPGA design of serial flash, speaking, reading and writing program source code
fr_regen
- 完成帧头的跨时钟处理，以减少信号的非周期性抖动等。-fr process
09_SDRAM_VGA_Display_Test640480
- 在quartusII的开发环境下，编写的VerilogHDL语言的SDRAM通信程序，欢迎下载，这是基于Crazybingo的板卡环境设计-Under the development environment of quartusII, write SDRAM VerilogHDL language communication program, welcome to download, this is based on Crazybingo board environment design