资源列表
lab4_1
- 时钟同步状态机模块化模板，点击转换信号则转换·至下一状态，设置有按键消颤-Clock synchronization state machine Modular template
lab3_1
- VHDL利用四位拨盘输入数据，输入两个数，显示于数码管，另两个数码管显示其取反，四个数字再留个数码管上以一秒为周期左移-VHDL use four dial input data, input two numbers displayed on the digital control, the other two digital display its negation, then leave a four-digit digital tube left at one-second cycle
uartsample
- Xilinx EDK开发 通过FPGA实现UART通信-EDK Xilinx development through FPGA to achieve UART communication
iic_src
- 标准I2C总线时序实现，可以用来初始化I2C设备。-Standard I2C bus timing implementation, can be used to initialize the I2C device。
IIC
- Verilog IIC程序，RAM接口，方便调试，一主多从-Verilog IIC program, RAM interface, easy to debug, and more a master
Random-sequence-of-test
- 随机序列的测试源码，使用verilog编写，感觉很有用，希望大家喜欢-Random sequence of test source, the use verilog to write, feel useful, I hope you like
tlv1544
- TLV1544的采集程序，使用verilog语言编写，感觉很实用，希望对大家有用-TLV1544 collection procedures, using verilog language, feel useful, hope to adopt
prj_button_anti_shake
- 按键消抖的fpga程序，code is based on verilog language, it is practical, we hope to help
urat
- rs232的verilog的代码，code is based on verilog language, it is practical, we hope to help
UART
- verilogHDL语言实现的uart模块，内部包含波特率生成、uart收、uart发三个子模块，支持配置常规波特率、数据位、结束位和校验位，输入工作时钟125M，时钟不一样时需要修改波特率生成的代码-verilogHDL language of uart module contains an internal baud rate generator, uart receive, uart made three sub-module, configured to support conventi
ps2_agreement
- 这是关于键盘和FPGA接口的协议的解读，中英文都有，非常详细，适合要写ps2接口的人-This is the interpretation of the Agreement on the keyboard and FPGA interfaces, the English have, in great detail, for people to write ps2 interface
ps2
- 这是采用了verilog 语言编写的ps2，也就是键盘和FPGA交互的端口协议，适用于virtex5-This is used ps2 verilog language, which is the keyboard port protocol and interactive FPGA for virtex5