资源列表
my_first_fpga
- 第一个FPGA程序的开发测试,用于DE1开发板的调试程序-The first FPGA development and testing program for debugging DE1 development board
jtd
- 基于verilog HDL描述的交通灯系统设计-Traffic Light System verilog HDL descr iption based
b2d
- 使用Verilog语言编写的2进制转10进制程序-Using Verilog language binary program turns 10 decimal
h2d
- 使用Verilog语言编写的16进制转10进制程序-Verilog language using hexadecimal decimal program turns 10
AD_sampling
- verilog TLC549采样控制程序-verilog TLC549 sampling control program
license
- Altera QuartusII V15.0
chuankou
- 基于fpga和stc15L408ad单片机的串口通信程序，一次可发送16位-Stc15L408ad based fpga and microcontroller serial communication procedures, one can send 16
PWM-Smart_CAR_Project
- FPGA循迹小车，可自回归，可进行PWM互补调速-FPGA car tracking, self-regression, can be complementary PWM Speed
Reed-Solomon-RS-ENCODE-DECODE
- 支持GF(2^n)域的rs编解码，可直接修改参数实现不同方式的RS编码和解码-This program is an encoder/decoder for Reed-Solomon codes.
lab3_2
- 加/减可调十六位计数器，可以清零，代码清晰-Plus/minus sixteen adjustable counter can be cleared, the code clear
lab3
- 数码管扫描电路，通过扫描数码管实现多个数码管同时显像功能-Digital scanning circuit, through digital scanning of multiple simultaneous digital imaging capabilities
lab4_2
- 脉冲宽度测量，按下按键开始脉冲宽度的测量，并设计有复位溢出信号，采用状态机模块化设计方法-Pulse width measurement, press the button to start measuring the pulse width, and the design of the overflow reset signal, using the state machine Modular Design