资源列表
ug195
- 这个文档是关于xilinx virtex-5 FPGA板的封装和管脚定义文件，对于使用v5 有很大的帮助-This document is package and pin definitions files about xilinx virtex-5 FPGA board for use v5 great help
RISC_cpu
- 一款8位的RISC-cpu 源码可在modelsim仿真出波形-An 8-bit RISC-cpu source code in modelsim simulation waveforms
0~99
- 通过VHDL语言编写的计数器，可以从0开始计数当计到99时再从0开始计数-Counter by VHDL language, you can start counting when the count 0 to 99 and then starts counting 0
quanjia
- 通过VHDL语言编写的一位全加器程序，该程序是经过元件例化的方式实现-VHDL language through a full adder program, which is the result of component instantiation way to achieve
yima
- 利用VHDL语言编写的译码程序，使用一位数码管进行显示-Using VHDL language decoding program that uses a digital display using VHDL language decoding program that uses a digital tube display
clk_even
- 利用FPGA编写的通用的偶分频，适合初学者使用-Even general division
adc0809_state
- 利用FPGA驱动DAC0832进行数据采样-Use FPGA drives DAC0832 sampling data
plj
- 频率计源代码，测量范围1hz-100Mhz，七位显示，三种量程，精度比较高-Frequency meter source code, measuring range 1hz-100Mhz, seven displays three range, high precision
Psoc-Design
- programmable silicon on chip documents
rc4
- RC4 is the most popular stream cipher in the domain of cryptology. RC4 consist of two algorithms Key Scheduling Algorithm (KSA) and Pseudo-random generation algorithm (PRGA).
adaptivefi-filter
- this code consists of adaptive fir filter algorithm using LMS based approach.
USB Interface IP Core
- This module implements data receiving and transfering with cooperation of PIDUSBD12