资源列表
QD_Tft43
- cpld+sram驱动tft 驱动4.3寸480x272分辨率的tft显示屏-Cpld+sram drive TFT drive 4.3 inch 480x272 resolution TFT display
crcmodule
- 这是一个FPGA的VHDL 高效CRC校验代码-This is an efficient FPGA-VHDL code for the CRC
AD_24bit_Group_25_CYC4
- 高精度24位ADC时钟配置和数据读取程序，基于Altera cyclone IV EP4CE22F17C6N-High-precision 24-bit ADC clock configuration and data reading program, based on Altera cyclone IV EP4CE22F17C6N
adc.v
- this an adc interface verilog code-this is an adc interface verilog code
111
- FPGA virtex5 串口通信并点亮LED灯显示-FPGA virtex5 serial communication and turn on the LED light display
MFSK.vhd
- 多进制数字频率合成系统VHDL程序,包含2进制、16进制。-Multi-band digital frequency modulation (MFSK) system VHDL program
VHDLstopwatch
- 采用vhdl硬件描述语言实现的秒表计时器程序源码及顶层电路设计图，实现了计时器，数码管显示，按键控制及蜂鸣器等功能-Using VHDL hardware descr iption language to realize the stopwatch timer program source code and top-level circuit design, the timer, digital tube display, control buttons and a buzzer functio
floatadd
- 32位浮点数加法，使用的语言是verilog。其中包括的是工程中的v文件。-32-bit floating-point addition, the use of language is verilog. Including is v of the engineering documents.
uart_tx
- UART 发送模块，UART底层的发送块，包含起始位，数据位，校验位，验证通过-UART transmit module，contain start bit，data bit，check bit. have passed verification
uart_rx
- UART 接收模块，UART底层模块，实现各种波特率的uart接收-UART receive module，complete all Baud rate transfer receive。
pcie_7x_v1_9
- PCIE控制器，FPGA实现PCIE通讯，速率高达5Gbps每个通道。-PCIT Controller ，Which speed up to 5G per lane
mig_7series_v1_9
- DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。-DDR3 Controller，complete DDR3 controll，have pass verificaion.