资源列表
v_ycrcb2rgb_v6_01_a
- Y C B C R 转 R G B 源 代 码-ycbcr to rgb source code
DIV
- 最新修改 veilog 除法器，32位除16位，输出数据锁存-//divider dividend divisor* quotient+ remainder //dividend 32 bit //divisor 16 bit //quotient 32 bit //remainder 32 bit //need 32 clk to finish the calculation //start 1 start the calculation //s
DHT11_verilog
- 基于FPGA的DHT11使用代码，本人已经调试过，可用。-FPGA-based DHT11 use the code, I have debugged and available.
UART_BACK_kc705
- xilinx的KC705串口收发程序，已上板验证过-UART program
fre(1000hz)
- 基于FPGA的频率发生器，晶振频率为48MHZ，输出频率为1000Hz，经过示波器检测，实际测得频率999.988HZ，误差在0.0012 -FPGA-based frequency generator, the crystal frequency is 48MHZ, the output frequency of 1000Hz, through the oscilloscope, the actual measured frequency 999.988HZ, error 0.0012
pci_to_wb_latest.tar
- PCI slave to WB master
cachecontroller_latest.tar
- This project is to develop a direct mapped cache controller for embedded applications. Key Design Features - Direct mapped with configurable address size, line size and number of cache lines - Non Pipelined architecture - No Cache f
arm_cache_sort
- ARM高速缓存(Cache)Verilog代码-ARM Cache Verilog
iic-BUS
- I2C/IIC 总线接口驱动，在Altera的FPGA上跑过，VHDL编写-I2C/IIC bus interface driver, running over the FPGA
mdio
- 用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件-Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file
Sparten6-CODE-_Verilog
- 基于xilinx 厂商的FPGA硬件的开发源代码，包括UART,SPI,以太网通信-The development of FPGA hardware based on xilinx manufacturers source code, including the UART, SPI, Ethernet communication and so on
10.2LCD_display-04
- 应用于车载系统娱乐设施，控制图像RGB数据在LCD屏上点屏，包括LCD的点屏时序控制，以及相关的LCD屏配置信息-Used in vehicle system entertainment facilities, control the RGB image data on the LCD screen, including point of LCD screen sequential control, and related LCD configuration information