资源列表
erfenpindevhdlyuveriloghdl
- 这是关于2分频的vhdl实现和verilog hdl实现，都已经仿真验证了其正确性，大家可以对比参考。
dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
shifter_left_8_8_4
- barrel shifter.实现循环左移的功能，8个输入，8个输出。每个输入或者输出是4位-barrel shifter. 8 inputs,8 outputs. And every input or output has 4bits.
kb_code
- keyboard interfacing
D_VHDL
- FPGA实现的触发器，VHDL描述，等等,可供参考-FPGA implementation of the trigger
ADC0809-digital-voltage-meter
- ADC0809简易数字电压表数码管显示c程序-ADC0809 digital voltage meter.
u_channel_correction
- 基于FPGA的通道不一致性校正的verilog代码-FPGA-based channel inconsistency correction verilog code
count5208
- baudrate for 9600 program
jiaotongdeng
- 本程序通过C语言实现交通灯模块，实现交通灯的控制。-The C language program through the traffic light module, the control of traffic lights.
GIOPHUTGIAY_DAUCHAM_573
- Card count time minutes seconds show led 7 segment
bin27seg_vhdl
- 采用VHDL编写的七段数码管显示程序-prepared using VHDL paragraph 107 of the procedures Digital Display
FPQ.rar
- 分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频,Divider vhdl descr iption of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency