资源列表
uart_rx_unpacked_0225_b
- 实现串口接收解包功能，包括启动，停止，复位，链路检测，位置环参数设置等功能。-Serial reception unpack functions including start, stop, reset, link detection, position loop parameter settings and other functions.
HD_top_null
- It s HD quad code . VHDL for Altera s cyclone4
dds_double_new
- FPGA用verilog语言编写的 dds程序，两路输出，频率可调，相位可调，输出波形可调-FPGA using verilog language dds program, two outputs, adjustable frequency, phase adjustable, adjustable output waveform
kejian2
- 是fpga方面的不错的课件，供大家参考，多提意见
lzrw1-compressor-core_latest.tar
- Lzrw1 压缩算法。spatan6上运行，有完整的仿真环境和代码testbench-Lzrw1 compression algorithm. runs on spatan6, a complete simulation environment and testbench code
tetris-FPGA
- 一款简单的俄罗斯方块游戏，用Verilog编写源码，方便大家学习-A simple tetris game, written in Verilog source, convenient for everybody to learn
src_0414
- 基于FPGA的乐曲发生器设计 -Design of FPGA-based music generator music generator design based on FPGA
Package
- Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 11
PCIE_DMA
- 实现了PCIE的接口，通过接口的实现，在此基础上实现了DMA数据传输。-PCIE interface, and on this basis through the implementation of the interface, the DMA data transfer.
ARMaFPGA
- ARM与FPGA结合的几十篇文章，非常有参考价值，工程师必备-ARM and FPGA combination of dozens of articles
synplify_ref_ug
- Synplify指导手册，内有vhdl、verilog、system verilog等综合详细指导，非常好的进阶资料喔！虽是英文的，但来自官方，绝对可靠喔！-Synplify guide, there vhdl, verilog, system verilog detailed, comprehensive guide, very good advanced data Oh! Although in English, but from the official, absolutely relia
pinlvji
- 数字频率计 实现对1Hz-10KHz频率信号的检测以及超量程警示-The digital frequency meter To detect the 1Hz-10KHz frequency signal and overrange alert