资源列表
mux_ovm_full-cover.tar
- this 4:1 mux verification code which is written in ovm and with functional coverage-this is 4:1 mux verification code which is written in ovm and with functional coverage
ynplify
- 详细介绍了syplify工具使用及其注意事项，对FPGA开发者很有帮助。-Described in detail syplify tool use and its attention to matters of the FPGA developers helpful.
EDA_usage
- 介绍最基础的概念，和用实例帮助理解，我受益很大-it dwell on concept in relation to vhdl and make sense of it by means of example
vhdl
- 这是一本关于VHDL方面的书籍，需要的网友可以下载来-This is an area of about VHDL books, users can download necessary to look at
c4gx_PCIe_gen1_x1
- 基于altera公司的cyclone4的pci-e源代码，非常好用，已经量产。-The altera Company a cyclone4 the pci-e source code, very easy to use, already in mass production.
usartV1.2
- 基于Verilog实现串口通讯，通过串口调试助手可测试(Serial communication based on Verilog, through the serial debugging assistant can test)
lab1
- 使用verilog HDL语言在FPGA上面实现LED闪烁控制，入门的一个基本程序(LED Scintillation control)
Exp3-Music
- 本次实验，是在 SOPC开发平台上实现一个音频信号发生器，将音箱接到开发平台上的 音频接口，由六个按键控制音箱发出 do、re、mi、fa、so、la 等音调，同时，编写几段音乐， 通过键盘选择，利用开发平台来播放几段音乐。 -The experiment is SOPC development platform to achieve an audio signal generator, the speaker received a development platform for th
21_ds1302
- 基于verilog HDL语言的模块程序，用于驱动ds1302时钟芯片-Based on verilog HDL language module program for driving ds1302 clock chip
CPU
- 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended
VHDL
- VHDL简明教程，对于想要学习VHDL的人是里面的资料相当不错，从初学到深入-Concise Guide to VHDL, VHDL for people who want to learn the inside information is quite good, from the beginner to the depth
EPM240
- 一些vhdl例子，希望大家喜欢，初学者还请多指教。-Some examples of vhdl I hope you like