资源列表
lcd
- LCD_1602(VHDL）显示自定义字符“贾”，显示通讯状态“send”和“recieve”，状态机，结构简单易读稳定，非常适合初学者。此程序已在altera开发板运行成功。-LCD_1602 (VHDL) custom character " Jia" , the communication status " send" and " recieve the state machine, easy-to-read structure stable, v
dengjingdu
- 数字频率计，2015国赛题目，可实现所有功能，整形电路无问题的话，测量结果几乎无误差！-Digital frequency meter, the 2015 National Games, can achieve all the functions, no problem of the plastic circuit, the measurement results are almost no error!
XILINX
- Xilinx ebook quick reference guide
LCD1602
- FPGA 1602显示，本人测试过，能用，希望您试试。-FPGA 1602
FPGAExamples
- A lot of usefull examples on VDHL lenguaje, includes VGA, Mouse, Keyboards, ADC, etc
jiyuFPGAdejiqirenshipinjianshixitong
- 基于FPGA的机器人视频监视系统，内有各种详尽的资料，绝对准确可靠！
AD9708
- 通过FPGA与AD9708高速DA模块输出可调频率的方波、正弦波、三角波，(Through FPGA and AD9708 high speed DA module, adjustable frequency Fang Bo, sine wave, triangle wave)
Report_JPEG-and-JPEG2000
- research paper on xilinx system gernator
21_ds1302
- 基于FPGA与DS1302时钟芯片采用Verilog HDL语言编写的数字时钟实现-Based on FPGA and DS1302 clock chip using Verilog HDL language of the digital clock to achieve
DDS
- 可以产生正弦波，三角波、锯齿波、方波，要求频率1Hz-100kHz，步进1Hz，具有自动扫频功能； 正弦波的相位可调，方波的占空比可调； -Can generate sine wave, triangle wave, sawtooth wave and square wave, the required frequency of 1 hz- 100 KHZ, step 1 hz, with functions of automatic frequency sweep The pha
QPSK_MODULATION
- 在quartus ii下完成的用VHDL语言编写的数字式调频系统QPSK-Accomplished in quartus ii the use of VHDL language QPSK digital FM system
fre
- verilog hdl 开发的频率计，运行环境 DE2-115开发板，内有modelsim仿真用的testbench。RTL级代码-verilog hdl developed frequency meter, operating environment, the DE2-115 development board, modelsim simulation of the testbench. RTL-level code