资源列表
timer
- 定时器功能，主函数。nios2 quartus-nios2 quartus main
TXd_FIFO
- 用FPGA 串口通信发送部分代码，FPGA芯片采用xilinx sptan3e 可以实现FPGA向通过max232电脑发送数据-The FPGA to send part of the code, serial communication, the FPGA chip using xilinx sptan3e can implement on FPGA send through max232 computer data
c8051_cfg
- 8051单片机设计主程序 顶层文件 顶层文件端口连接-8051 design of the main top-level file
Ram_FIFO
- 同步fifo 适合学生使用 深度为十六 适合刚入门的学生联系堆栈-sys fifo
AX301_led_test_code
- 黑金AX301开发板led相关实验程序代码-AX301 development board LED test code
7
- verilog 写的 “梁祝”乐曲演奏电路-verilog wrote " The Butterfly Lovers" music concert circuit
serial_implementation
- VHDL 实现 有限冲击响应滤波器的设计（串行式）-VHDL realization of finite impulse response filter design (Serial)
sell
- 基于FPGA的自动售饮料机，包含2.5元、3元两种选择-FPGA-based beverage vending machines, including 2.5, 3 yuan two options
fsmd_debounce_exp
- vhdl debounce circuit
VHDL-test-code-general-register
- VHDL实验代码：通用寄存器组，这是一个基于VHDL开发的程序，非常的实用-VHDL test code: general register, which is a VHDL-based development process, a very practical
Digital-Clock
- FPGA数字跑表代码 Digital Clock-Digital Clock