资源列表
SDRAMping-pong-memory-structure
- 双口RAM 的乒乓存储结构（芯片型号CY7C09279） 应用场合为FPGA向双口RAM不断写入数据，PCI总线从RAM读取数据。[已调试验证]-Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging
firtesmul
- 基于FPGA的FIR滤波器实现，并行乘法实现，运行速率快但占用资源多。-FPGA-based FIR filter, parallel multiplication achieve faster run rate but take up more resources.
CLOCK-CODE-VHDL
- VHDL源码程序，功能完整的时钟电路代码-using ALTERA s FPGA design, QUARTUS software development platform.VHDL CARD,
CIC_DEC_4
- CIC抽取滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC decimation filter design, CIC filter order 4 times using 5 samples.
vhdl
- LED控制,实现LED功能！源代码！8.2 .3程序设计与仿真 例1：FPGA驱动LED静态显示 --文件名：decoder.vhd --功能：译码输出模块，LED为共阳接法 -LED controls, LED function to achieve! Source code! .3 8.2 programming and simulation case 1: FPGA driving LED static display- File Name: decoder.vhd- Fu
fpga-chengxu
- 对扩频通信系统的仿真程序，应用于fpga开发环境下-a simulation of Spread spectrum communication, using for fpga environment
final
- 洗衣机正反转控制程序，用于洗衣机驱动器的控制-key
ComparatorTestVersion
- 基於wire方式設計的補償器,但需外接DFF依照同學想做幾階的可在進行外加,Z^-1 需2個 Z^-2 3個依此類推.僅提供實做參考,實際參數需自行設計-Based on wire mode compensator design, but need to add DFF in accordance with the order of a few students want to be carrying plus, Z ^-1 need two Z ^-2 3 one, and so on. Pr
Gen_Square
- 利用DDS技术产生100~1MHz的方波 利用DDS技术产生100~1MHz的方波-generate 100Hz ~ 1MHz square with DDS,using verilog HDL generate 100~1MHz square with DDS,using verilog HDL generate 100~1MHz square with DDS,using verilog HDL
adc_ltc238016
- LTC238016fa VHDL execution code
Synchronous_read_write_RAM
- Synchronous read write RAM verilog。经过modelsim se仿真。
keyboard
- 用VHDL语言实现4*4键盘的识别，扫描键盘，译码并点亮开发板上相应led-4*4keyboard，VHDL