资源列表
DE3_340_USB
- de3 fpga开发板实现SD读写功能，友晶公司源代码-de3 fpga finish the sd test
FPGA 正交编码 verilog
- 用Verilog写的2倍频率正交编码的仿真测试程序，仿真波形已经调出
Divider
- xilinx 除法ip核调用 含测试程序 vhdl语言-xilinx ip nuclear division calls including test procedures vhdl language
i2c
- 该压缩包包含了i2c core设计所需的详细时序说明书以及用verilog编写的core的源代码、仿真模块。-The archive contains the i2c core design specifications required for the detailed timing and preparation of the core with the verilog source code, the simulation module.
i2c
- 该压缩包包含了i2c core设计需要的文献资料以及verilog编写实现i2c通信的源代码-The archive contains the i2c core design requires the preparation of literature and the verilog source code to achieve i2c communication
Divider
- 除法的fpga实现 开发环境ise 语言vhdl-divider ise vhdl fpga
DE2_70_SD_Card_Audio_Player
- DE2播放音乐，包含文件系统，帮助开发MP3。-DE2 music, including the file system.
timing
- Verilog实现计数器并送六位数码管实时显示(Verilog realize the counter and send six digital tube real-time display)
SHA256_SYSTEM
- 利用硬件（可编程逻辑器件FPGA）实现密码算法SHA256，在FPGA中嵌入软核NIOSii，在NIOSii上进行软件编程。 硬件EDA工具为ALTERA的Quartus ii，软件IDE为eclipse（嵌在Quartua中）。(The hardware (programmable logic device FPGA) is used to implement the cryptographic algorithm SHA256, and the soft core NIOSii is em
jtd
- 基于verilog HDL描述的交通灯系统设计-Traffic Light System verilog HDL descr iption based
usb_rd_buffer
- FPGA（SPARTAN6）通过USB协议与开发板上的USB芯片进行数据读写测试，在上位机上可以看到USB发来的数据，也可以通过修改VERILOG代码完成数据的接收(FPGA (SPARTAN6) can read and write data through the USB chip on the development board through the USB protocol. The data sent by USB can be seen on the host computer,
Bonus-Lab-Test-Version-draft6
- Verilog implementation of 8 bit computer for FPGA