资源列表
CIC_verilog
- 采用verilog实现的三级CIC抽取器，输入8位数据，输出26位数据，使用有限状态机用于实现下采样，包括积分器实现模块和梳状器实现模块-Using verilog to achieve three CIC decimation filter, the input 8-bit data output 26-bit data, the use of finite state machines for sampling, including the integrator and comb to im
RS(204-188)decoder_verilog
- 采用verilog实现的有限域GF(28)弱对偶基乘法器，本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ，多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7}，弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}-Verilog achieved using the finite field GF (28) weak dual basis multiplier
verilog_cordic
- 采用verilog编写的经典的cordic算法，旋转模式，亲测可用，经过了9次旋转-Classic verilog prepared by the cordic algorithm, rotation mode, pro-test available, after nine rotation
syn_wr
- 一般来说，CPU的读写时钟会引入到PLD中，笔者利用CPU的读写时钟实现同步读写寄存器，提高设计的可靠性。因此这种建模方式是推荐的CPU读写PLD寄存器建模方式-In general, CPU clock reading and writing will be introduced to the PLD, the author uses the CPU to read and write clock synchronized read and write registers, improve d
if_single
- 所以从语法上讲，多if语句（if... if… if…）可以建模具有优先级的条件判断结构；而单if语句（if...else if…else if…）和case语句可用于建模不带优先级的条件判断。但是随着综合工具优化能力的不断增强，新型的综合工具大多时候会自动优化掉优先级结构，以减少芯片面积，提高时序性能。另外，条件结构的综合结果是否带有优先级不但取决于综合工具的类型和版本，还和目标器件或目标库有直接关系-Therefore, grammatically, and more if statemen
syn_rst
- 指定同步复位时， always的敏感表中仅有时钟沿信号，仅仅当时钟沿采到同步复位的有效电平时，才会在时钟沿到达时刻进行复位操作-Specifies synchronous reset, always sensitive to the table is just a clock edge signal only when the clock along to pick active level synchronous reset, the clock edge arrival time will
srl2pal
- 数据流串并转换的实现方法多种多样，根据数据的排序和数量的要求，可以选用移位寄存器、RAM等来实现。对于数据量比较小的设计来说，可以使用移位寄存器完成串并转换；对于排列顺序有规定的串并转换，可以用case语句判断实现；对于复杂的串并转换，还可以用状态机实现-Serial data stream and converts a variety of implementations, according to the sort and quantity of data requirements, you
FFT
- 使用Verilog硬件描述语言实现信号处理中的FFT信号的变换-Using Verilog hardware descr iption language conversion signal processing FFT signal
LED
- 基于VHDL语言，利用Vivado开发的16位跑马灯-A 16-running-lights program based VHDL which is developed by vivado
dds
- 数字频率合成器设计，可实现各种频率正弦波的生成，亲测可用-Digital frequency synthesizer designed to achieve a variety of frequency sine wave generator, pro-test available
nco-cos
- 余弦波发生器，利用vhdl仿真软件可以产生余弦波图像-Cosine wave generator, the use of VHDL simulation software can generate cosine wave images
nco_sin
- 正弦波发生器，利用quarter ii编译仿真可以产生正弦波图像-Sine wave generator, using quarter ii compile simulation can generate sine wave images