资源列表
uart
- 用VHDL实现的一个uart控制器，输入时钟为33M-Use VHDL to achieve a UART controller, input clock for the 33M
pwm-c
- 用VHDL编写的PWM控制程序，通过寄存器控制20余路PWM输出；qar是quartus的压缩包格式-VHDL prepared using PWM control procedures, through the registers to control more than 20 road PWM output qar is Quartus compressed packet format
Veriloghuangjincankaozhinan
- Verilog 黄金参考指南是Verilog 硬件描述语言及其语法语义合并以及将它应用到硬件设计的一个 简明的快速参考指南-Verilog Golden Reference Guide is the Verilog hardware descr iption language and its syntax and semantics combined it applied to hardware design, a concise Quick Reference Guide
JIANCHE
- 本设计是一个序列检测器，能够检测11位长的系列信号，根据需要可适当扩展其序列长度-The design is a sequence detector, can detect a long series of 11 signals, according to the needs may be appropriate to expand its sequence length
jishuqi
- 本文十一个计数器的实验报告，阐述了设计的思路，设计的具体方案，以及上机操作的步骤，描述非常详细！-This article counters 11 Experimental report on the design ideas, design specific programs, as well as steps on the machine, described in great detail!
pinlvji
- 本文十一个用VHDL频率计设计的方案描述，该设计阐明了设计的思路，步骤以及设计的最终代码，设计方案十分详细，是您学习的必备辅助！-In this paper, with 11 Cymometer VHDL design program descr iption, the design sets out design ideas, steps and design the ultimate code, the design is very detailed, it is essential tha
shuzizhong2008
- 本文描述了数字钟的设计方案和具体的设计步骤及代码，功能比较全面，可以直接用作课程设计！-This paper describes the design of digital clock program and the specific design steps and code, function more comprehensive and can be directly used for curriculum design!
4weishuzipinlvjikongzhimokuai
- Verilog HDL下的4 位数字频率计控制模块源代码-Verilog HDL under four digital frequency meter control module source code
v2c5_sopc_leds
- FPGA中NIOS2led显示程序，非常适合初学者-FPGA in NIOS2led display program very suitable for beginners
kbclj
- 可编程逻辑系统的VHDL设计技术，早期经典的VHDL教程，以CYPRESS器件为基础，希望对大家有所帮助！-Programmable Logic VHDL system design technology, early classic VHDL Guide to CYPRESS device based on the hope that all of you to help!
16_FIR
- 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
VHDLxianjie
- VHDL语言详解，简要全面的介绍vhdl要点-Detailed VHDL language, VHDL, introduced a comprehensive summary points