资源列表
pipeline
- 使用VERILOG實現MIPS2000的PIPELINE-Use VERILOG realized MIPS2000 the PIPELINE
CX40_Code
- 某公司的驱动TFT LCD的测试代码,使用VHDL，ISE环境-A company' s drive TFT LCD test code
ise_book
- VHDL学习资料，大量example可供参考学习，应用。-VHDL study
Arithmetic_blok
- Fast arithmetic bloc.
Intro_to_Digital_Design-Digilent-Verilog_Online.z
- Nice Book for Verilog Basics
SystemVerilogCheatSheet
- System verilog book for common systax use
LCD1602
- LCD1602液晶显示 整体显示关光标不闪烁-LCD1602 LCD The cursor does not blink the whole display off
UART-Verilog-source
- Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test
VHDL
- 正弦波发生器代码VHDL 其中包括分频 正弦波数据-Sine wave generator VHDL code Divide the sine wave data including
Digital-display
- 数码管显示实现代码 共阳极显示 从0-F十六进制显示-Digital display implementation code Common anode display From 0-F hexadecimal display
Divider
- VHDL代码实现分频器设计 分频器系统时钟20万分频 上升沿触发-VHDL code Divider Design The system clock frequency divider 20 extremely Rising edge triggered
i2c2
- 基于FPGA的verilog实现i2c协议通信，本人亲测能够很好实现-base on FPGA verilog i2c